LG

April 6, 2005

 

Status of Prototype Ladder Development

 

We report on the status of the prototype ladder development with reference to the plan developed late last year and linked here. http://www.lbnl.leog.org/Pixel_Prototype_Testing.pdf

 

We have constructed 3 prototype ladders. The original intention was to construct one prototype with a set of staged additions cumulating in a finished prototype. This turned out to be not easily possible with the existing mechanical fixtures for detector placement. The fixtures, as constructed, is adequate for doing an accurate placement of 10 detectors but not well suited to placing individual detectors in the correct position. This led to the creation of prototype #1 which had 9 detectors placed on the prototype cable mounted on a RVC/CFC beam. We ran into problems troubleshooting 9 bonded detectors so another prototype was constructed and in-house wire-bonding capability was acquired. An additional prototype was constructed to allow 2 people to work independently.

 

Prototype Ladder Status

 

We now have 3 prototype ladders.

 

Ladder 1 –

 

Construction – CFC/RVC/CFC carrier, cable, 9 x 50 µm MIMOSA5 detectors, 3 detectors (all 4 sectors) instrumented with amplifiers and differential drivers.

 

Status – This prototype was damaged during construction and 3 of the MIMOSA5 detectors are chipped or cracked. The MIMOSA5 detector in position 8 (2nd detector from the right) returns ROWMK. The rest are not yet tested fully and the board needs modification of the wire bonding and surface mount electronics to be tested further.

 

Ladder 2 –

 

Construction – CFC/RVC/CFC carrier, cable, 3 x 50 µm MIMOSA5 detectors, 2 detectors (all 4 sectors) instrumented with amplifiers and differential drivers.

 

Status – This prototype is the one that we are using to read multiple detectors out over the cable and into the motherboard / ADC-memory daughter card. The MIMOSA5 detectors in positions 10 and 8 are wire bonded and instrumented with drivers. The detectors are yellow graded chips and each has 2 working sectors.

 

 

 

Ladder 3 –

 

Construction – bakelite carrier, cable, 1 x 50 µm MIMOSA5 detector, 1 detector (all 4 sectors) instrumented with amplifiers and differential drivers.

 

Status – This prototype is the one that we first successfully read out over the cable and into the motherboard / ADC-memory daughter card. The MIMOSA5 detector in position 10 is wire bonded and instrumented with drivers. The detector is graded green but has only 2 working sectors. The other sectors are damaged somehow and draw a large amount of current. Some data was taken before the bond wires to that sector melted.

 

Motherboard and ADC/memory Daughter Card Status

 

 

 

We have constructed 1 motherboard and 2 daughter cards. Some layout errors were discovered and patched around with the result that the system is now functional but not as easily reconfigurable due to the necessary patching. We are taking data read out from the card through a LVDS connection to a custom PCI card in a LINUX PC. The functional schematic is shown below.

 

Development on the CDS in VHDL on the daughter cards in ongoing. We will post links to the data soon.

 

Status of Prototype Ladder Testing With Respect to the Testing Plan

 

From the previously linked document we have the following testing goals with the status.

 

Stage 1 – prototype goals

  1. Cable performance with 1 detector – This has been successfully tested and the performance, while not yet quantified, appears to be the same as with the testing done with a MIMOSA bonded to our single chip mezzanine card.
  2. Mechanical assembly with 1 detector / bonding – This has been successfully accomplished.

 

 

Stage 2 – prototype goals

  1. Cable performance with multiple detectors. – This is currently under investigation and will be quantified. Initial results look good.
  2. New MB performance - This is currently under investigation and will be quantified. Initial results look good. We are testing the MB, daughter card and overall system performance and will be reporting on it as soon as results are generated.
  3. New daughter card performance – See above.
  4. VHDL CDS performance – This is under development. We will post results as they are generated.
  5. Overall system performance – See above.
  6. Mechanical assembly with multiple detectors / bonding. – The mechanical assembly done uncovered some needed additional precautions in handling and identified new fixturing that will need to be constructed for producing individual MIMOSA prototypes. For producing finished ladders, the fixturing is appropriate.
  7. Alignment techniques. – The alignment techniques tested through the fixturing seem quite good. Some additional mechanical model ladders were construcred with red graded MIMOSA chips and some of the alignments and mechanical properties checked. A first look can be found here. http://www.lbnl.leog.org/crossing_lines_measurement_first_look.htm
  8. Cooling system design and performance. – This has not yet been examined. We will do these tests with the mechanical model ladders.
  9. Beam test? – not yet.

 

Lessons Learned and Current Questions

 

  1. Handling – The CFC/RVC carriers with their 50 µm MIMOSA detectors are actually quite fragile. During the construction of the 1st prototype ladder, the ladder was dropped as it was removed from a pressure chamber used to properly fix the film adhesive. The small fall (~10cm) broke at least 3 of the Detectors and damaged the carrier. We will be developing improved handling techniques that help keep this type of accident from happening.
  2. Fixturing – The fixturing used for producing the 9 MIMOSA prototype and the mechanical model ladders worked well. The fixtures were not designed, however, for individual installation of MIMOSAs into an existing array. This should not have been necessary in out original plan but became necessary as we ran out of usable working MIMOSAs to install and had to install and place by hand. New fixturing will be designed and manufactured if we need to add more detectors to the existing ladders.
  3. Orcad MIMOSA5 chip definition – The Orcad definition of the pad layout on the chip that was used to produce the cable has an error. This required that we change the wire bonds. Fortunately the error only required an offset of 1 pad for 8 wire bonds. This error will be corrected.
  4. gain adjustments – We have optimized the gain in a particular MIMOSA to match the ADC that we are using. Testing some other bonded detectors, we find that the gain is somewhat off for these chips. We will keep looking for an optimized compromise for all, or apply individual gain settings to each chip.
  5. ROWMK – Only 1 chip output such as ROWMK may be attached to the output bus. Any unpowered MIMOSA (or even powered ones, in our experience) will keep the buss pulled down.
  6. Reference Voltages – The chip reference voltages are currently being set to 2.5V with a resistor divider consisting of 2 5K ohm resistors. The input impedance of the voltage reference inputs is significantly low with respect to the 5K resistors used. In addition, the input impedance seems to vary between chips so some of our reference voltages are not what we would like. There is some evidence that the impedance is also dependant on what is happening in the chip. We need to study this further and possibly add a buffer to keep this input stable and at the correct voltage.
  7. Motherboard Layout – An error was made in the layout of the motherboard that resulted in the mirror imaging on the daughter card sockets. Since most of the signals are differential, we were able to adapt without heroic efforts but this and a few other errors need to be corrected. This will make it hard to do a complete 5 daughter card test without making a new motherboard. We will correct this.