Design Overview for hft_daughtercard_top

PropertyValue
Project Name:c:\sxm\sxm\sxm\als_27_1\hft_xilinx71
Target Device:xc2v1000
Report Generated:Saturday 04/28/07 at 05:35
Printable Summary (View as HTML)hft_daughtercard_top_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers:6,14610,24060% 
Number used as Flip Flops:6,143   
Number used as Latches:3   
Number of 4 input LUTs:6,94410,24067% 
Logic Distribution:    
Number of occupied Slices:5,1185,12099% 
Number of Slices containing only related logic:4,7235,11892% 
Number of Slices containing unrelated logic:3955,1187% 
Total Number 4 input LUTs:8,27010,24080% 
Number used as logic:6,944   
Number used as a route-thru:1,323   
Number used as Shift registers:3   
Number of bonded IOBs:27232483% 
Number of Block RAMs:304075% 
Number of GCLKs:101662% 
Number of DCMs:3837% 
Number of RPM macros:4   

Performance Summary

PropertyValue
Final Timing Score:289919
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:186

Failing Constraints (total failing = 186)

Constraint(s)RequestedActualLogic Levels
* NET "RST" MAXDELAY = 1 ns 1.000ns1.612ns 
* NET "daq_inst/adc_inst/IntFrameFrom2To3P"MAXDELAY = 1 ns 1.000ns1.380ns 
* NET "daq_inst/adc_inst/IntFrameFrom2To3N"MAXDELAY = 1 ns 1.000ns1.246ns 
* NET "daq_inst/adc_inst/AdcCh3/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns 0.550ns0.655ns 
* NET "daq_inst/adc_inst/AdcCh3/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns 1.010ns1.619ns 
* NET "daq_inst/adc_inst/AdcCh3/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns 1.010ns1.625ns 
* NET "daq_inst/adc_inst/IntFrameFrom1To2P"MAXDELAY = 1 ns 1.000ns1.546ns 
* NET "daq_inst/adc_inst/IntFrameFrom1To2N"MAXDELAY = 1 ns 1.000ns1.257ns 
* NET "daq_inst/adc_inst/AdcCh2/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns 0.550ns0.655ns 
* NET "daq_inst/adc_inst/AdcCh2/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns 1.010ns1.614ns 
* NET "daq_inst/adc_inst/AdcCh2/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns 1.010ns1.618ns 
* NET "daq_inst/adc_inst/AdcCh1/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns 0.550ns0.655ns 
* NET "daq_inst/adc_inst/AdcCh1/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns 1.010ns1.623ns 
* NET "daq_inst/adc_inst/AdcCh1/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns 1.010ns1.623ns 
* TS_daq_inst_adc_inst_inst_adc_dcm_CLK0_BUF_0 = PERIOD TIMEGRP "daq_inst_adc_inst_inst_adc_dcm_CLK0_BUF_0" TS_ADC_LCLK_P HIGH 50% 3.333ns6.922ns1
* TS_daq_inst_adc_inst_inst_adc_dcm_CLK180_BUF_0 = PERIOD TIMEGRP "daq_inst_adc_inst_inst_adc_dcm_CLK180_BUF_0" TS_ADC_LCLK_P PHASE 1.667 ns HIGH 50% 3.333ns6.638ns1
* TS_dcm50to100_inst_U2_CLKDV_BUF = PERIODTIMEGRP "dcm50to100_inst_U2_CLKDV_BUF" TS_dcm50to100_inst_U1_CLK2X_BUF / 2LOW 50% 20.000ns29.096ns13
* COMP "RAM_DQ<10>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns12.218ns0
* COMP "RAM_DQ<11>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.217ns1
* COMP "RAM_DQ<12>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.252ns1
* COMP "RAM_DQ<13>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.223ns1
* COMP "RAM_DQ<14>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.208ns1
* COMP "RAM_DQ<15>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.207ns1
* COMP "RAM_DQ<20>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.510ns1
* COMP "RAM_DQ<16>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.202ns1
* COMP "RAM_DQ<21>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.501ns1
* COMP "RAM_DQ<17>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.236ns1
* COMP "RAM_DQ<22>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.169ns1
* COMP "RAM_DQ<18>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.204ns1
* COMP "RAM_DQ<23>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.168ns1
* COMP "RAM_DQ<19>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.201ns1
* COMP "RAM_DQ<24>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.171ns1
* COMP "RAM_DQ<25>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.168ns1
* COMP "RAM_DQ<30>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.230ns1
* COMP "RAM_DQ<26>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.196ns1
* COMP "RAM_DQ<31>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.202ns1
* COMP "RAM_DQ<27>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.195ns1
* COMP "RAM_DQ<32>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.218ns1
* COMP "RAM_DQ<28>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.204ns1
* COMP "RAM_DQ<33>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.247ns1
* COMP "RAM_DQ<29>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.201ns1
* COMP "RAM_DQ<34>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.213ns1
* COMP "RAM_DQ<35>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.212ns1
* COMP "RAM_DQ<40>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.229ns1
* COMP "RAM_DQ<36>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.220ns1
* COMP "RAM_DQ<41>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.226ns1
* COMP "RAM_DQ<37>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.217ns1
* COMP "RAM_DQ<42>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.233ns1
* COMP "RAM_DQ<38>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.225ns1
* COMP "RAM_DQ<43>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.230ns1
* COMP "RAM_DQ<39>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" 12.000ns13.222ns1
Please refer to Place and Route Report for complete list of failing constraints.   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentSaturday 04/28/07 at 05:30
Translation ReportCurrentSaturday 04/28/07 at 05:30
Map ReportCurrentSaturday 04/28/07 at 05:31
Pad ReportCurrentSaturday 04/28/07 at 05:33
Place and Route ReportCurrentSaturday 04/28/07 at 05:33
Post Place and Route Static Timing ReportCurrentSaturday 04/28/07 at 05:34
Bitgen ReportCurrentSaturday 04/28/07 at 05:35