Constraint(s) | Requested | Actual | Logic Levels |
* NET "RST" MAXDELAY = 1 ns | 1.000ns | 1.612ns | |
* NET "daq_inst/adc_inst/IntFrameFrom2To3P"MAXDELAY = 1 ns | 1.000ns | 1.380ns | |
* NET "daq_inst/adc_inst/IntFrameFrom2To3N"MAXDELAY = 1 ns | 1.000ns | 1.246ns | |
* NET "daq_inst/adc_inst/AdcCh3/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns | 0.550ns | 0.655ns | |
* NET "daq_inst/adc_inst/AdcCh3/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns | 1.010ns | 1.619ns | |
* NET "daq_inst/adc_inst/AdcCh3/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns | 1.010ns | 1.625ns | |
* NET "daq_inst/adc_inst/IntFrameFrom1To2P"MAXDELAY = 1 ns | 1.000ns | 1.546ns | |
* NET "daq_inst/adc_inst/IntFrameFrom1To2N"MAXDELAY = 1 ns | 1.000ns | 1.257ns | |
* NET "daq_inst/adc_inst/AdcCh2/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns | 0.550ns | 0.655ns | |
* NET "daq_inst/adc_inst/AdcCh2/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns | 1.010ns | 1.614ns | |
* NET "daq_inst/adc_inst/AdcCh2/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns | 1.010ns | 1.618ns | |
* NET "daq_inst/adc_inst/AdcCh1/TheTime/IntRiseFfP" MAXDELAY = 0.55 ns | 0.550ns | 0.655ns | |
* NET "daq_inst/adc_inst/AdcCh1/TheRec/IntRxDatInP" MAXDELAY = 1.01 ns | 1.010ns | 1.623ns | |
* NET "daq_inst/adc_inst/AdcCh1/TheRec/IntRxDatInN" MAXDELAY = 1.01 ns | 1.010ns | 1.623ns | |
* TS_daq_inst_adc_inst_inst_adc_dcm_CLK0_BUF_0 = PERIOD TIMEGRP "daq_inst_adc_inst_inst_adc_dcm_CLK0_BUF_0" TS_ADC_LCLK_P HIGH 50% | 3.333ns | 6.922ns | 1 |
* TS_daq_inst_adc_inst_inst_adc_dcm_CLK180_BUF_0 = PERIOD TIMEGRP "daq_inst_adc_inst_inst_adc_dcm_CLK180_BUF_0" TS_ADC_LCLK_P PHASE 1.667 ns HIGH 50% | 3.333ns | 6.638ns | 1 |
* TS_dcm50to100_inst_U2_CLKDV_BUF = PERIODTIMEGRP "dcm50to100_inst_U2_CLKDV_BUF" TS_dcm50to100_inst_U1_CLK2X_BUF / 2LOW 50% | 20.000ns | 29.096ns | 13 |
* COMP "RAM_DQ<10>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 12.218ns | 0 |
* COMP "RAM_DQ<11>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.217ns | 1 |
* COMP "RAM_DQ<12>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.252ns | 1 |
* COMP "RAM_DQ<13>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.223ns | 1 |
* COMP "RAM_DQ<14>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.208ns | 1 |
* COMP "RAM_DQ<15>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.207ns | 1 |
* COMP "RAM_DQ<20>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.510ns | 1 |
* COMP "RAM_DQ<16>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.202ns | 1 |
* COMP "RAM_DQ<21>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.501ns | 1 |
* COMP "RAM_DQ<17>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.236ns | 1 |
* COMP "RAM_DQ<22>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.169ns | 1 |
* COMP "RAM_DQ<18>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.204ns | 1 |
* COMP "RAM_DQ<23>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.168ns | 1 |
* COMP "RAM_DQ<19>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.201ns | 1 |
* COMP "RAM_DQ<24>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.171ns | 1 |
* COMP "RAM_DQ<25>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.168ns | 1 |
* COMP "RAM_DQ<30>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.230ns | 1 |
* COMP "RAM_DQ<26>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.196ns | 1 |
* COMP "RAM_DQ<31>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.202ns | 1 |
* COMP "RAM_DQ<27>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.195ns | 1 |
* COMP "RAM_DQ<32>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.218ns | 1 |
* COMP "RAM_DQ<28>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.204ns | 1 |
* COMP "RAM_DQ<33>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.247ns | 1 |
* COMP "RAM_DQ<29>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.201ns | 1 |
* COMP "RAM_DQ<34>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.213ns | 1 |
* COMP "RAM_DQ<35>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.212ns | 1 |
* COMP "RAM_DQ<40>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.229ns | 1 |
* COMP "RAM_DQ<36>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.220ns | 1 |
* COMP "RAM_DQ<41>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.226ns | 1 |
* COMP "RAM_DQ<37>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.217ns | 1 |
* COMP "RAM_DQ<42>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.233ns | 1 |
* COMP "RAM_DQ<38>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.225ns | 1 |
* COMP "RAM_DQ<43>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.230ns | 1 |
* COMP "RAM_DQ<39>" OFFSET = OUT 12 ns AFTER COMP "CLK_p" | 12.000ns | 13.222ns | 1 |
Please refer to Place and Route Report for complete list of failing constraints. | | | |