Design Overview for clustergeneratorfake

PropertyValue
Project Name:c:\sxm\sxm\sxm\leo40\hft_xilinx71
Target Device:xc2v1000
Report Generated:Friday 02/23/07 at 15:27
Printable Summary (View as HTML)clustergeneratorfake_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:2210,2401% 
Number of 4 input LUTs:510,2401% 
Logic Distribution:    
Number of occupied Slices:115,1201% 
Number of Slices containing only related logic:1111100% 
Number of Slices containing unrelated logic:0110% 
Total Number 4 input LUTs:2210,2401% 
Number used as logic:5   
Number used as a route-thru:17   
Number of bonded IOBs:3932412% 
Number of GCLKs:1166% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentMonday 02/05/07 at 20:09
Translation ReportCurrentMonday 02/05/07 at 20:09
Map ReportCurrentMonday 02/05/07 at 20:09
Pad ReportCurrentMonday 02/05/07 at 20:09
Place and Route ReportCurrentMonday 02/05/07 at 20:09
Post Place and Route Static Timing ReportCurrentMonday 02/05/07 at 20:09
Bitgen ReportCurrentFriday 02/23/07 at 15:27