The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design myfifo.vhd. The design myfifo.vhd has a depth of 16384 words of 32 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.
The above waveform shows the behavior of the design under normal read and write conditions with aclr .